1. Field of Invention
The present invention relates generally to network systems. More particularly, the present invention relates to lower data rate telecommunication modules which conform with the Small Form Factor Pluggable Transceiver Multisource Agreement (SFP-MSA) standard.
2. Description of the Related Art
The demand for data communication services is growing at an explosive rate. Much of the increased demand is due to the fact that more residential and business computer users are becoming connected to the Internet. To address the demand for data communication services, the use of optical networks, such as a synchronous optical network (SONET), is becoming more prevalent. A SONET network is an example of a time division multiplexed (TDM) network. TDM networks generally allocate single lines to be used amongst multiple users, or customers of data communication services. The single lines may each be divided into slots of time during which each user has access to the single lines.
The types of traffic being carried by the Internet are shifting from lower bandwidth applications towards high bandwidth applications which include voice traffic and video traffic. Since different users may require equipment to transmit and receive traffic associated with different data rates, many vendors provide equipment which supports a variety of different data rates. The equipment which supports a variety of different interfaces often includes pluggable modules, e.g., optical modules, which vary depending upon the type of service the equipment is to support. For example, pluggable modules may be chosen based on data rates which are anticipated, and based on whether signals are expected to be long haul or short haul.
In order to enable optical modules, e.g., transceivers, to be readily swapped into and out of equipment, standard form factors for such modules are typically defined. When modules have the same form factors, the ability to configure equipment to meet changing needs is enhanced, as it becomes a relatively simple matter to replace one module with another. The Small Form-Factor Pluggable Transceiver Multisource Agreement (SFP-MSA) standard, which is incorporated herein by reference in its entirety, is one standard to which pluggable interfaces may conform. The SFP-MSA standard specifies dimensions and pinouts for a pluggable transceiver module that supports standards for fiber optic systems such as Asynchronous Transfer Mode (ATM), FDDI, Fiber Channel, Fast Ethernet, Gigabit Ethernet, SONET, and Synchronous Digital Hierarchy (SDH) applications.
The SFP-MSA standard generally defines twenty pin positions and functions that are to be used by pluggable interfaces which are in compliance with the SFP-MSA standard. FIG. 1 is a diagrammatic representation of the twenty pins specified in the SFP-MSA standard. A connector block 90 which is suitable for use on a host board (not shown) or a SFP transceiver includes pins 100 which are typically oriented such that pins 100a-j are positioned facing towards a bezel (not shown) associated with the host board and pins 100k-t are positioned facing towards an application specific integrated circuit (ASIC) or other circuitry (not shown) on the host board.
A first pin ‘VEET’ 100a, a seventeenth pin ‘VEET’ 100q, and a twentieth pin ‘VEET’ 100t are transmitter grounds, while a sixteenth pin ‘VCCT’ 100p is a transmitter power pin. Ninth, tenth, and eleventh pins ‘VEER’ 100i-k, as well as fourteenth pin ‘VEER’ 100n are receiver grounds, while a fifteenth pin ‘VCCR’ 100o is a receiver power pin.
A second pin ‘TX FAULT’ 100b is a transmitter fault indication pin, and is an open collector or drain output which, when low, indicates normal operation of an sfp-MSA compliant module plugged into connector block 90. Hence, ‘TX FAULT’ 100b is a status line associated with a module plugged into connector block 90. A third pin ‘TX DISABLE’ 100c is a transmitter disable pin, and is a control line from a host board (not shown) to a module plugged into connector block 90 which enables the transmitter optical output of the module to be shut down or otherwise disables as needed.
Fourth, fifth, and sixth pins ‘MOD-DEF( )’ 100d-f are module definition pins which may be used to enable the module interfaced with connector block 90 to be substantially identified. A seventh pin ‘RATE-SELECT’ 100g is a control line from a host board (not shown) to a module plugged into connector block 90 which enables a selection to be made between a full receiver bandwidth and a low receiver bandwidth. An eighth pin ‘LOS’ 100h is a loss of signal pin and, hence, is a status line. LOS 100h is an open collector or a drain output which, when low, is arranged to indicate that a module plugged into connector block 900 is operating normally.
A twelfth pin ‘RD-’ 1001 and a thirteenth pin ‘RD+’ 100m are differential receiver outputs, while an eighteenth pin ‘TD+’ 100r and a nineteenth pin ‘TD−’ 100s are differential transmitter outputs. ‘RD−’ 1001 and ‘RD+’ 100m are a differential pair of lines that terminate at the deserializer of the host board's SERDES (not shown), while ‘TD+’ 100r and ‘TD−’ 100s are a differential pair of lines that effectively terminate at the serializer of the host board's SERDES (not shown).
In general, differential lines such as those associated with ‘RD−’ 1001 and ‘RD+’ 100m are high speed data lines, or data lines which are suitable for carrying Gigabit Ethernet traffic or Fiber Channel traffic. Such high speed data lines effectively terminate at a SERDES on a host board, while other lines associated with an SFP module may bypass the SERDES. FIG. 2 is a diagrammatic representation of an SFP module which is interfaced in a connector block of a host board. An SFP module 200 which is “plugged into” or otherwise interfaced with a connector block 210 of a host board. As shown, while control lines associated with a ‘TX DISABLE’ pin 210 and a ‘RATE-SELECT’ pin 212, as well as status lines associated with a ‘TX FAULT’ pin 214 and an ‘LOS’ pin 216, substantially bypass a SERDES 220, high speed data lines 218 associated with SFP module 200, e.g., a line associated with a ‘RD-’ pin and a line associated with a ‘RD+’ pin, are substantially connected to SERDES 220.
In some instances, users may wish to use low speed transceiver modules, as for example for T1/E1 or T3/E3 interfaces, in addition to high speed modules. By way of example, if a user uses one or more high speed SFP modules to aggregate Gigabit Ethernet signals into a 2.5 Gigabit Trunk circuit, they may also wish to use one or more low speed SFP modules to transmit and receive PBX data along with the Gigabit Ethernet signals on the same trunk. While dedicated lower speed data lines could be used to transmit and to receive the PBX data, obtaining those lower speed data lines may be much more expensive than sharing high speed trunk bandwidth that might otherwise be effectively wasted.
A data path designed for gigabit rate services such as Fiber Channel or Gigabit Ethernet typically has a termination at a SERDES which has clock and data recovery (CDR), as previously mentioned. Since a SERDES generally has a limited frequency range that may only operate at frequencies of down to approximately thirty megahertz (MHz), the SERDES generally does not operate as intended for signals with some low speed frequencies associated with telecommunication, herein and after “telecom,” interfaces such as T1 and T3. Further, since line interface chips, as for example line interface units (LIUs) that are commonly available for interface to T1 and T3 telecom interfaces convert line signals to a pair of single ended clock and data signals in a transmit direction and a receive direction, signals associated with T1 and T3 telecom interfaces are generally incompatible with the differential pair data path of the SFP-MSA standard.
Although logic may be added to an SFP transceiver module to convert separate clock and data signals created by an LIU into single combined differential pair signals, such logic often proves to be expensive to implement. In addition to adding cost to the manufacturing of SFP transceiver modules, adding logic to SFP transceiver modules that converts separate clock and data signals into single combined differential pair signals may cause the size of the SFP transceiver modules to be significantly increased, when components associated with such logic may not fit into typically small SFP transceiver modules.
Therefore, what is desired is a method and an apparatus for enabling low speed data paths through SFP-MSA modules. More specifically, what is needed is a system which makes it possible for lower data rate telecom interfaces such as T1/E1 and T3/E3 interfaces to be used on SFP compliant transceiver modules.